1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a protective film of a plasma display panel and a fabricating method thereof that are adaptive for reducing a jitter value of an address period.
2. Description of the Related Art
Generally, a plasma display panel (PDP) excites and radiates a phosphorus material using an ultraviolet ray generated upon discharge of an inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe, to thereby display a picture. Such a PDP is easy to be made into a thin-film and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development.
Referring to FIG. 1, a discharge cell of a conventional three-electrode, AC surface-discharge PDP includes a sustain electrode pair having a scan electrode Y and a sustain electrode Z provided on an upper substrate 1, and an address electrode X provided on a lower substrate 2 in such a manner to be perpendicular to the sustain electrode pair.
Each of the scan electrode Y and the sustain electrode Z consists of a transparent electrode and a metal bus electrode thereon.
On the upper substrate 1 provided with the scan electrode Y and the sustain electrode Z, an upper dielectric layer 6 and a MgO protective film 7 are disposed. The MgO protective film 7 plays a role to protect a sputtering of particles generated by a discharge as well as enhance an emission effect of secondary electrons.
A lower dielectric layer 4 are formed on the lower substrate 2 provided with the address electrode X in such a manner to cover the address electrode X. Barrier ribs 3 are formed vertically above the lower dielectric layer 4. A phosphorous material 5 is coated onto the surfaces of the lower dielectric layer 4 and the barrier ribs 3.
The upper substrate 1 is joined to the lower substrate by means of a sealant (not shown). An inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe is injected into a discharge space provided among the upper substrate 1, the lower substrate 2 and the barrier ribs 3.
Such a PDP makes a time-divisional driving of one frame, which is divided into various sub-fields having a different emission frequency and adopts an address display separated (ADS) system in which an addressing is separated from a display, so as to realize gray levels of a picture. Each sub-field is again divided into a reset period for initializing the entire field, an address period for selecting a scan line and selecting the cell from the selected scan line and a sustain period for expressing gray levels depending on the discharge frequency. The reset period is divided into a set-up interval supplied with a rising ramp waveform and a set-down interval supplied with a falling ramp waveform.
For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) is divided into 8 sub-fields SF1 to SF8 as shown in FIG. 2. Each of the 8 sub-field SF1 to SF8 is divided into a reset period, an address period and a sustain period as mentioned above. Herein, the reset period and the address period of each sub-field are equal for each sub-field, whereas the sustain period and the number of sustain pulses assigned thereto are increased at a ratio of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field.
FIG. 3 and FIG. 4 show driving waveforms of the PDP shown in FIG. 1.
Referring to FIG. 3, the PDP is divided into a reset period, an address period and a sustain period for its driving.
In the reset period, a rising ramp waveform Ramp-up is applied to all the scan electrodes Y in a set-up interval SU. A discharge is generated within the cells of the full field with the aid of the rising ramp waveform Ramp-up. By this set-up discharge, positive wall charges are accumulated onto the address electrode X and the sustain electrode Z while negative wall charges are accumulated onto the scan electrode Y.
After a set-up discharge, a falling ramp waveform Ramp-down falling from a positive voltage lower than a peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes Y. The falling ramp waveform Ramp-down causes a weak erasure discharge within the cells to erase a portion of excessively formed wall charges. Wall charges enough to generate a stable address discharge are uniformly left within the cells with the aid of the set-down discharge.
In the address period, a negative scanning pulse scan is sequentially applied to the scan electrodes Y and, at the same time, a positive data pulse data is applied to the address electrodes X in synchronization with the scanning pulse scan. A voltage difference between the scanning pulse scan and the data pulse data is added to a wall voltage generated in the reset period to thereby generate an address discharge within the cells supplied with the data pulse data. Wall charges enough to cause a discharge when a sustain voltage is applied are formed within the cells selected by the address discharge.
Meanwhile, a positive direct current voltage Zdc is applied to the sustain electrodes Z during the set-down interval and the address period. The direct current voltage Zdc causes a set-down discharge between the sustain electrode Z and the scan electrode Y, and establishes a voltage difference between the sustain electrode Z and the scan electrode Y or between the sustain electrode Z and the address electrode X so as not to make a strong discharge between the scan electrode Y and the sustain electrode Z in the address period.
In the sustain period, a sustaining pulse sus is alternately applied to the scan electrodes Y and the sustain electrodes Z. Then, a wall voltage within the cell selected by the address discharge is added to the sustain pulse sus to thereby generate a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied.
Just after the sustain discharge was finished, rectangular waves ers1 and ers2 having a small pulse width and a ramp waveform ers3 having a low voltage level are applied to the sustain electrode Z as erasure signals for erasing electric charges within the cell. If such erasure signals ers1, ers2 and ers3 are applied within the cell, then an erasure discharge occurs to thereby erase wall charges generated by the sustain discharge and left.
Driving waveforms shown in FIG. 4 is different from driving waveforms shown in FIG. 3 in that an initialization waveform applied in the reset period should be rectangular waves rst1, rst2 and rst3 and a rising ramp waveform Ramp-up applied alternately to the scan electrode Y and the sustain electrode Z. Further, signals applied to each electrode X, Y and Z during the address period and the sustain period are substantially identical to those shown in FIG. 3.
In order to implement a high picture quality, such a PDP requires a high definition, a high brightness, a high contrast ratio and a low contour noise, etc. Also, in order to implement a high picture quality, the PDP assures an appropriate address period in the ADS driving system. Since the number of lines to be scanned is increased as the PDP develops into a higher definition/higher resolution, the address period is lengthened and an assurance of the sustain period becomes difficult. For instance, when 480 scan lines exist; a scanning time of 3 μs per line is required; a single scan system in which the scan lines are scanned sequentially from the first scan line until the last line is adopted; and a driving is made with one frame being divided into eight sub-field, an address period required within one frame becomes more than 480×3 μs×8=13 ms. Thus, a time to be assigned in the sustain period within one frame becomes (16.67 ms–13 ms) which is absolutely insufficient. A scanning time must be reduced so as to assign a time more than such an insufficient sustain period, but it is difficult to reduce an address period because a width of the scanning pulse is defined largely in consideration of a jitter upon address discharge. The jitter is a discharge delay time generated upon address discharge. The jitter has some differences for each sub-field and has a certain range upon driving. Since the scanning pulse includes such a jitter value, the pulse of the scanning pulse width becomes longer. Accordingly, since the address period becomes longer as a jitter value goes larger, it becomes difficult to implement a high picture quality. The jitter value is liable to be more increased as a temperature or an neighbor temperature of the PDP goes lower. This forces the PDP to make an unstable address discharge at a low temperature. Thus, since a miss writing causing a failure of cell selection occurs to emerge a black noise on a displayed picture, an environment confrontation ability is deteriorated. In the mean time, Japanese Patent Laid-open Gazette No. 2001-135238 has suggested a PDP wherein a content of Xe in a discharge gas sealed within the PDP is increased into more than 5 volume %, thereby allowing a higher driving voltage and a much higher brightness in comparison to the conventional low-density Xe panel. However, a high-density Xe panel has a larger jitter value of the address period as a content of Xe goes higher. Accordingly, it is difficult to implement a high-density Xe panel due to such a jitter value of the address period.
A factor making a largest affect to a jitter value of the address period is a secondary electron emission characteristic of the protective film 7. Since a jitter is more reduced as a secondary electron emission efficiency of the protective film 7 goes higher and hence a pulse width of the scanning pulse is reduced by the reduced jitter value, it is possible to shorten the address period.